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Ordering number : EN4542A
CMOS LSI
LC8903, 8903Q
Digital Audio Interface Receiver
Overview
The LC8903 and LC8903Q are receiver LSIs for applications in which data is transmitted between digital audio equipment in the EIAJ format. These LSIs synchronize with the input signal and demodulate that signal to a regular format signal.
Package Dimensions
unit: mm 3025B-DIP42S
[LC8903]
Features
* Built-in PLL circuit synchronizes with the input EIAJ format signal. * Microprocessor interface receives mode settings and outputs fs codes, copy information, and category codes. * Supports both 384 fs and 512 fs system clocks (selectable) and provides 256 fs, 128 fs, BCLK and LRCK clock outputs. * Can operate in either digital source mode or analog source mode. * Validity flag output * User bit CD subcode interface * DIP42S and QIP44M packages * Silicon gate CMOS process, single 5 V power supply
SANYO: DIP42S
unit: mm 3148-QFP44MA
[LC8903Q]
SANYO: QIP44MA
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
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93094TH VL-0945, 0946/81793HK No. 4542-1/15
LC8903, 8903Q Application Usage Overview Diagram When both digital source mode and analog source mode are used
Digital source mode: EIAJ CP-1201 format data reception mode Analog source mode: Analog data is received and converted to digital for signal processing.
This figure shows an example of a structure using the LC8903/Q. In analog source mode the only function of the LC8903/Q is to provide control clocks. Pin Assignments
Top view Top view
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Maximum I/O voltages Operating temperature Storage temperature Symbol VDD max VI*VO max Topr Tstg Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 -30 to +75 -55 to +125 Unit V V C C
No. 4542-2/15
LC8903, 8903Q Allowable Operating Ranges
Parameter Supply voltage Operating temperature Symbol VDD Topg Conditions min 4.5 -30 typ 5.0 max 5.5 +75 Unit V C
DC Characteristics at Ta = -30 to +75C, VDD = 4.5 to 5.5 V
Parameter Input high level voltage Input low level voltage Input high level voltage Input low level voltage Input high level voltage Input low level voltage Output high level voltage Output low level voltage Current drain Input amplitude Note: 1. 2. 3. 4. Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH VOL IDD VPP *1 *1 *2 *2 *3 *3 IOH = -1 A IOL = 1 A VDD = 5.0 V, Ta = 25C, input data fs = 48 kHz *4 10 0.4 20 Conditions min 2.2 -0.3 0.7 VDD -0.3 0.8 VDD -0.3 VDD - 0.05 VSS + 0.05 30 VDD + 0.3 typ max VDD + 0.3 +0.8 VDD + 0.3 0.3 VDD VDD + 0.3 0.2 VDD Unit V V V V V V V V mA V
Input pins other than DIN1, DIN2, DIN3, DIN4, RC1 and XMODE. TTL compatible. XIN pin. CMOS compatible. The XMODE and RC1 pins. CMOS Schmitt inputs. The condition prior to the capacitors on the DIN1, DIN2, DIN3 and DIN4 input pins.
AC Characteristics at Ta = -30 to +75C, VDD = 4.5 to 5.5 V
Parameter Output pulse width Output setup time Output data hold time Output delay (high) Output delay (low) Symbol tWBO tDSO tDHO tbdH tbdL Conditions fs = 48 kHz, with a 30 pF load capacitance min 160 80 80 -10 -10 0 0 +10 +10 typ max Unit ns ns ns ns ns
Note: 5. When validity is output from the V/DOUT2 pin.
No. 4542-3/15
LC8903, 8903Q Microprocessor Interface Block AC Characteristics at Ta = -30 to +75C, VDD = 4.5 to 5.5 V
Parameter CL low level pulse width CL high level pulse width Data setup time Data hold time CL rise time CL fall time CE delay time CL delay time Data delay time CL, data delay time CL delay time CL, CE delay time Symbol TWL TWH TDS TDH Tr Tf TD1 TD2 TD3 TD4 TD5 TD6 With a 30 pF load capacitance With a 30 pF load capacitance 100 1.0 CL, CE, DI CL, CE, DI 1.0 50 25 50 Conditions min 100 100 50 50 30 30 typ max Unit ns ns ns ns ns ns s ns ns ns ns s
No. 4542-4/15
LC8903, 8903Q CD Subcode Interface AC Characteristics at Ta = -30 to +75C, VDD = 4.5 to 5.5 V
Parameter SBSY block frequency SBSY pulse width SFSY frame frequency SFSY high level pulse width SFSY low level pulse width SBCK high level pulse width SBCK low level pulse width SBCK rise time SBCK fall time SBCK delay time P data access Data hold time Symbol tB tBW tF tFHW tFLW tCHW tCLW trC tfC tCD tPAC tHD 0 *8 10 20 3 *8 *8 *6 *7 Conditions min 12.0 110 90 4 1.5 2.0 2.0 4.0 4.0 5.0 5.0 30 30 30 10 136 165 typ 13.3 max 14.7 Unit ms s s s s s s ns ns s s s
Note: Assumes that the load capacitance on each output pin is 30 pF.
No. 4542-5/15
LC8903, 8903Q The LC8903 and LC8903Q use the subcode synchronization word and the start bit in the user bits for subcode interface system timing extraction. Therefore, SBSY and SFSY change depending on that timing. Keep the following notes on user bit transfer in mind when using the values of tBW, tF, tCHW, tCLW and tCD within the specifications described above. Basically, user bit transfers must follow the table shown here.
Note: 6. Subcode synchronization is taken as a block synchronization section (the start of a block) when a minimum of 22 consecutive data bits are zero. 7. The frame sync signal S0 period is 90.7 s. The S1 period also has a minimum value of 90.7 s (when there are 22 consecutive zero data bits), depending on the subcode sync word period. 8. When the shortest user data word length is used, the SBCK signal delay (tHD) and pulse widths (tCHW and tCLW) must be set below their typical values.
No. 4542-6/15
LC8903, 8903Q Pin Functions
Pin No. QIP 1 2 3 4 DIP 6 7 8 9 Symbol DIN5 DOUT1 V/DOUT2 RC1 I/O I O O I Function Data input. There is no built-in amplifier on this pin. EIAJ data through output Validity flag output Alternatively, the microprocessor interface can set this pin to output the EIAJ input data unchanged. RC oscillator input This circuit generates a clock used to detect incorrect PLL locking and to reset the PLL system. RC oscillator output This pin outputs a clock with a frequency of about 40 kHz when the component values specified in the sample application circuit are used. CLKOUT2 output clock switching: Low = 256 fs, high = 128 fs Clock mode switching: Low = 384 fs, high = 512 fs Test pin (Should be tied low in normal operation.) Used to start system operation after power is applied. Digital power supply Analog power supply I VCO oscillator band adjustment Analog ground I O VCO free-running setting PLL low-pass filter Digital system ground O O O I Subcode interface block sync signal Subcode interface data output Subcode interface frame sync signal Subcode interface bit clock input Digital power supply I O O O O Crystal oscillator input Crystal oscillator output Crystal oscillator and VCO clock output 256 fs and 128 fs clock output Error mute signal output Digital ground O O O O O O O I I I Sampling frequency output Bit clock output Audio data output Left/right clock output High = emphasis on, low = emphasis off. Outputs a low level in analog mode. Microprocessor interface output Microprocessor interface input Microprocessor interface chip enable input Microprocessor interface clock input Digital power supply I I I I Digital ground Data inputs with built-in amplifiers
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
10 11 12 13 14 15 -- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -- 32 33 34 35 36 37 38 39 40 41 42 1 2 3 4 5
RC2 CLKMD CLK TEST1 TEST2 XMODE DVDD AVDD R AGND VIN VCO DGND SBSY PW SFSY SBCK DVDD XIN XOUT CLK OUT1 CLK OUT2 ERROR DGND SUB1 SUB2 BCLK DATA OUT LRCK EMPHA DO DI CE CL DVDD DIN1 DIN2 DIN3 DIN4 DGND
O I I I I I
No. 4542-7/15
LC8903, 8903Q Block Diagram
Clock Modes The LC8903/Q CLKOUT1 and CLKOUT2 output clock modes are selected by the CLK and CLKMD pins according to the table.
CLK L H CLK MD L H CLK OUT1 384 fs clock output 512 fs clock output CLK OUT2 256 fs clock output* 128 fs clock output
Note: * When the CLK pin is low, the 256 fs clock duty has a high to low ratio of 2:1.
No. 4542-8/15
LC8903, 8903Q Microprocessor Interface The microprocessor interface is used for specifying the data input pin, for setting the output data format, and for specifying subcode output, system stop, and analog source mode. The figure shows the interface I/O formats. Microprocessor Interface Formats
Address The bits B0 to A3 in the format figure are the address. There are two addresses allocated to the LC8903/Q, one for input and one for output. The microprocessor must specify the input address to input data and the output address to output data. Address Code
Mode Data input Data output B0 H L B1 L H B2 H H B3 L L A0 L L A1 H H A2 H H A3 L L
Microprocessor Interface Input 1. Input pin and validity output settings The DIN1 to DIN4 data input pins have built-in amplifiers and can accept signals with levels of about 400 mVp-p. DIN5 is a special-purpose input pin for optical input.
The data input system multiplexer is controlled by inputs from the microprocessor interface. The table shows the relationship between the code in bits I5 to I13 in the microprocessor interface format and the data demodulation outputs DOUT1 and V/DOUT2. V is output from the V/DOUT2 pin.
No. 4542-9/15
LC8903, 8903Q
I5 I6 I7 Data demodulation input I8 I9 I10 DOUT1 I11 I12 I13 DOUT2 L L L DIN1 L L L DIN1 L L L V H L L DIN2 H L L DIN2 H L L DIN1 L H L DIN3 L H L DIN3 L H L DIN2 H H L DIN4 H H L DIN4 H H L DIN3 L L H DIN5 L L H DIN5 L L H DIN4 H L H XSYS H L H GND H L H DIN5 L H H XSYS L H H GND L H H GND H H H XSYS H H H GND H H H GND
Note: Setting the data demodulation input code to one of the XSYS settings switches the system clock from the VCO to the crystal oscillator and sets the LC8903/Q to analog source mode. Selecting one of the input pins once again sets the LC8903/Q to digital source mode and PLL operation.
2. Data output mode setting There are two data output modes: 16-bit MSB first and 20-bit msb first. These are selected by the bit I14 code.
I14 Data output mode L 16-bit MSB first H 20-bit MSB first
3. System stop The operation of both the VCO and the crystal oscillator can be stopped, thus stopping the whole LC8903/Q system, by setting the bit I4 code as shown in the table.
I4 -- L System operation H System stop
The values of the bits I4 to I14 are all initialized to low immediately after the XMODE pin goes from low to high. Since bits I0 to I3 and I15 are not used, their initial values are undefined. Microprocessor Interface Output Bits D0 to D15 in the microprocessor interface output format have the following meanings.
Bit D0 D1 D2 D3 D4 D5 to D12 D13 to D15 Function Invalid bit. Always output as a low level. Indicates the sample frequency. Corresponds to the fs external output pin. Indicates the state of the copy flag. High = copy enabled, low = copy protect Outputs the first bit of the channel status bits. These pins output the channel status 8-bit category codes serially. Invalid bits. Always output as low levels.
No. 4542-10/15
LC8903, 8903Q Interpretation of the D1 and D2 bits
Sampling frequency D1 D2 32 kHz H H 44.1 kHz L L 48 kHz L H #1 H L
Note: 1. The "#1" value indicates either a PLL lock error or analog source mode. In these states the data is cleared and bits D0 and D3 to D15 are all set to low. 2. D1 and D2 are in the "#1" state in the initial values of the codes immediately after the XMODE pin goes from low to high. All other codes are set to low. 3. The interval between one microprocessor data readout operation and the next must be 6 ms or longer.
FS Output Code The SUB1 and SUB2 pins indicate the input data sampling frequency.
Sampling frequency SUB1 SUB2 32 kHz H H 44.1 kHz L L 48 kHz L H #1 H L
Note: The "#1" value indicates PLL lock error or analog source mode. When SUB1 and SUB2 have these values, the DATAOUT and EMPHA pins will output low levels.
CD Subcode Interface The LC8903 and LC8903Q use the SFSY, SBCK, PW and SBSY pins to output the CD subcode data. This data is the user bits that were transferred according to the CP-1201 interface format and converted to a format that conforms to the CP-2401 interface format. The timing is shown in the figures.
The timing of the rising and falling edges of the SFSY signal is changed according to the timing of the start bits in the input data user bits as shown in the figure.
No. 4542-11/15
LC8903, 8903Q Errors 1. ERROR pin: This pin goes high when there are errors in the input data or when the PLL circuit is unlocked. When data demodulation returns to normal, the high level is held for about 200 to 300 ms and then the ERROR pin goes low. This time is inversely proportional to the fs of the input data. 2. Data processing when an error occurs: The table lists the data processing performed when an error occurs.
Error Type Up to 8 consecutive parity errors Nine or more consecutive parity errors PLL lock error Audio Output Data Previous data value output Data with the value zero is output. Data with the value zero is output. Retained Retained Data is cleared and the "#1" state is indicated. FS Output Code Output Output Cleared, and a low level output. V Flag
Note: Preamble detection is used to recognize PLL lock errors.
Analog Source Mode The LC8903 and LC8903Q switch to analog source in the following two cases. 1. When analog source mode is selected by the data sent over the microprocessor interface 2. When there is no signal on the input pin selected for data demodulation In analog source mode, the clock that runs the whole system is supplied by the crystal oscillator clock and the PLL circuit and data demodulation are stopped. The BCLK, LRCK, CLK, OUT1 and CLKOUT2 clocks are output. The output pins function as follows in analog source mode. * DOUT1, V/DOUT2 Data specified through the microprocessor interface is output. * ERROR The lock error state high level is output. * SUB1, SUB2 The "#1" lock error state code is output. * DATAOUT The lock error state low level is output. * EMPHA, V flag The lock error state low level is output. * Microprocessor interface codes Input codes: The code values set through the microprocessor interface are retained. Output codes: Values identical to those for a PLL lock error are output. Crystal Oscillator 1. The presence or absence of data is determined by an internal detection circuit. This circuit operates on either the VCO or the crystal oscillator clock. When power is first applied, the clock is supplied from the VCO, and the LC8903 and LC8903Q switch to the crystal oscillator if a no data state is detected. Here, if a clock signal was not supplied from the crystal oscillator after a no data state is detected, the whole system would stop and remain in the stopped state, since the detection circuit would not operate even if data were supplied. 2. The XIN and XOUT pins include a built-in oscillator amplifier circuit, and take on the following states when a crystal oscillator is connected.
Pin XIN XOUT Data Present* High Low Data Absent Accepts crystal oscillator input. Outputs the inverted state of the XIN pin.
Note: * The XIN pin is pulled-up internally when the LC8903/Q is in the data present state.
No. 4542-12/15
LC8903, 8903Q XMODE The XMODE pin resets the LC8903 and LC8903Q system. The LC8903 and LC8903Q will start to function normally if a high level is applied to this pin after the power supply voltage rises above a value of at least 4.5 V.
1. Once the LC8903 and LC8903Q is operating, the system will be reset if a low level is applied once again to the XMODE pin. 2. This IC can be used without using the microprocessor interface by tying the CE, CL and DI microprocessor interface input pins low and using D1 as the data input pin. This technique can be used as a simplified method for product evaluation. Data Output Timing The figures show the data output timing. 1. Data is output in synchronization with the falling edge of the BCLK signal. 2. Data, BCLK and LRCK are output in synchronization with the rising edge of the 256 fs clock. 3. The data output timings for 20-bit MSB first and 16-bit MSB first output are shown in the timing charts. Timing Chart
No. 4542-13/15
LC8903, 8903Q Sample Application Circuit
Circuit Constants
Item Symbol R1 R2 R3 Resistors R4 R5 R6 R7 R8 Value 33 k 10 k 24 k 5.6 k 5.6 k 120 to 150 200 200 k Capacitors Item Symbol C1 C2 C3 C4 C5 C6 Value 1000 pF 10 to 100 F 0.1 F 0.01 F 10 to 47 pF 10 to 47 pF
No. 4542-14/15
LC8903, 8903Q Input Pin Application Circuits
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any and all SANYO products described or contained herein fall under strategic products (including services) controlled under the Foreign Exchange and Foreign Trade Control Law of Japan, such products must not be exported without obtaining export license from the Ministry of International Trade and Industry in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of August, 1998. Specifications and information herein are subject to change without notice. PS No. 4542-15/15

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